1. Field of the Invention
The present invention relates to a circuit which includes a DCFL (Direct Coupled FET Logic) circuit configured with a depletion-mode FET or an enhancement-mode FET and which controls a current supplied from a voltage booster circuit.
2. Description of the Background Art
As is already known, a voltage booster circuit is a circuit for boosting an external power supply voltage and generating a voltage higher than the external power supply voltage. The voltage booster circuit is increasingly integrated into a semiconductor circuit. Further, various types of GaAs (gallium arsenide) monolithic microwave integrated circuits (MMIC) each incorporating the voltage booster circuit have been proposed for the sake of improvements in high-frequency characteristics and in response to a recent tendency toward a low voltage.
In the case of a semiconductor integrated circuit including the voltage booster circuit, a boosted voltage to be outputted from the voltage booster circuit is determined in accordance with a current supply capacity of the voltage booster circuit and a current supplied to a circuit connected to the voltage booster circuit. Accordingly, in order to boost the voltage efficiently, it is necessary to increase the current supply capacity of the voltage booster circuit, or to decrease the current supplied to the circuit connected to the voltage booster circuit. To increase the current supply capacity of the voltage booster circuit leads to an increase in a chip size and also to an increase in a consumption current, and thus is not effective means. Therefore, it is most important to decrease the current supplied to the circuit connected to the voltage booster circuit.
In the semiconductor integrated circuit including the voltage booster circuit, a logic circuit, which controls the boosted voltage boosted by the voltage booster circuit or which converts a voltage level of a signal into the boosted voltage, may be used as the circuit connected to the voltage booster circuit. For example, see Japanese Laid-Open Patent Publication No. 7-321638.
A conventional logic circuit for controlling the boosted voltage or converting a voltage will be described. FIG. 9 is a diagram showing a conventional logic circuit 110 including an inverter circuit (logic gate) INV configured with an enhancement-mode FET or a depletion-mode FET. FIG. 10 is a diagram showing a conventional logic circuit 120 in which an output drive circuit DR is provided at a stage subsequent to the inverter circuit INV so as to increase a load driving capacity at a stage thereafter. For example, see Japanese Laid-Open Patent Publication No. 7-074619.
In the conventional logic circuit 110, a high level voltage signal or a low level voltage signal is inputted to an input terminal IN. The voltage booster circuit CP boosts a voltage inputted from an external power supply terminal VDD, and a resultant boosted voltage is outputted from a boosted voltage supply terminal VCP. A load R is configured with a resistance element, the depletion-mode FET, and the like. A transistor EF1 is a drive transistor and configured with the enhancement-mode FET, and is located between the load R and a grounding voltage source VSS (e.g., 0V).
When a high level voltage (e.g., 0.7V) is inputted to the input terminal IN, the transistor EF1 enters a conduction state, and the inverter circuit INV outputs a low level voltage (e.g., 0V). On the other hand, when the low level voltage is inputted to the input terminal IN, the transistor EF1 enters an blocked state, and the inverter circuit INV outputs the boosted voltage (e.g., 7V).
Further, the conventional logic circuit 120 includes the inverter circuit INV similar to that in the logic circuit 110 and an output drive circuit DR constituting a push-pull circuit. The output drive circuit DR includes a pull-up transistor EF2, and a pull-down transistor EF3, each of which is configured with the enhancement-mode FET.
When the high level voltage (e.g., 0.7V) is inputted to the input terminal IN, the transistor EF1 enters the conduction state, and the inverter circuit INV outputs the low level voltage (e.g., 0V). In response to the output, the transistor EF2 enters the blocked state and the transistor EF3 enters the conduction state, and thus the output drive circuit DR outputs the low level voltage (0V). On the other hand, when the low level voltage is inputted to the input terminal IN, the transistor EF1 enters the blocked state, and the inverter circuit INV outputs the boosted voltage (e.g., 7V). In response to the output, the transistor EF2 enters the conduction state, and the transistor EF3 enters the blocked state, and thus the output drive circuit DR outputs the boosted voltage (7V).
The conventional logic circuit 120 shown in FIG. 10 has the push-pull type output drive circuit DR placed at the stage subsequent to the inverter circuit INV, and thus the load drive capacity at the time of outputting the boosted voltage can be increased.
However, the above-described conventional logic circuits 110 and 120 which use the DCFL circuit configured with the enhancement-mode or depletion-mode FET so as to control the boosted voltage or to convert the voltage have the following problem.
When the low level voltage is inputted to the input terminal IN, and the transistor EF1 is in the blocked state, the current hardly flows from the boosted voltage supply terminal VCP to the grounding voltage source VSS, and thus the current is hardly consumed by the inverter circuit INV. Accordingly, the current supplied from the boosted voltage supply terminal VCP is determined in accordance with the load connected to the output terminal OUT.
However, when the high level voltage is inputted to the input terminal IN, and the transistor EF1 is in the conduction state, a current supplied from the voltage booster circuit CP becomes equal to the current which flows from the boosted voltage supply terminal VCP to the grounding voltage source VSS and which is consumed by the inverter circuit INV, since the transistor EF1 is the enhancement-mode FET. That is, in the conventional logic circuits 110 and 120, while the high level voltage is inputted to the input terminal IN, the current flows through the transistor EF1 constantly.
That is, the boosted voltage outputted from the voltage booster circuit CP is determined in accordance with a total output current supplied to a plurality of logic circuits connected to the voltage booster circuit CP. Accordingly, in the case where the logic circuit is configured with the enhancement-mode FET or the depletion-mode FET, an unnecessary current needs to be supplied from the voltage booster circuit CP, compared to a case where the logic circuit is configured with a MOS transistor, and consequently a decrease in the boosted voltage may be caused.
In order to solve the problem, a method is considered in which the load R of the inverter circuit INV is adjusted, whereby the current supplied from the voltage booster circuit CP is reduced when the high level voltage is inputted to the input terminal IN. However, the method of reducing the current with the use of the load R of the inverter circuit INV may cause an increase in a chip area and also cause a delay in switching time, and thus the method is not effective.